1. Field of the Invention
The present invention relates to a high melting point solder alloy superior in oxidation resistance, in particular a solder alloy provided with both a high oxidation resistance and high melting point suitable as a through hole filling material for forming through hole interconnects.
2. Description of the Related Art
In recent years, remarkable advances have been made in the integration and reduction of size of CPUs, memories, acceleration and angular velocity sensors, and other semiconductor devices. Further, advances in microelectromechanical systems (MEMS) have led to commercialization of products in new fields such as micromirrors combining optical switches, optical waveguides, and other optical devices and semiconductor devices.
In view of this, with the aim of further increasing the speed, improving the performance, reducing the size, and lightening the weight of devices, studies have been made on increasing the density of systems by stacking a plurality of 3D chips on silicon (Si) substrates, glass substrates (SiO2 based etc.), or combinations of the two.
At this time, with conventional stacked mounting using wire bonding, there are limits to the shapes and numbers of the chips which can be stacked. Further, with structures stacking thin packages via interposers and connecting external leads of the individual packages, the limits on the number of stacked layers are greatly eased, but if the number of stacked layers is increased, the length of the interconnects between chips end up increasing.
As opposed to this, if forming through hole interconnects connected passing through a silicon substrate or other substrate, the limit on the number of stacked layers can be eliminated and the increase of the interconnect length can be avoided.
A silicon substrate or glass substrate can reduce the thermal stress and thermal strain between the chip and substrate since it has a coefficient of heat expansion close to the IC chip or other silicon functional chip mounted. Further, it is also advantageous for mounting a CPU or other chip accompanied with a large heat emission due to the high heat conductivity.
Further, even with a single silicon device with no stacking, for example, even with a device such as an image sensor where it is desired to make the effective area of the detector as large as possible, the package size can be greatly reduced by taking out the terminals at the back of the substrate by through hole interconnects.
To make such through hole interconnects, through holes are filled with electroconductive materials. In the past, electroconductive paste has been widely used as a through hole filling material (for example, Japanese Unexamined Patent Publication (Kokai) No. 2000-138432, Japanese Unexamined Patent Publication (Kokai) No. 2000-138434, and Japanese Unexamined Patent Publication (Kokai) No. 2000-219811), but the fillable through hole aspect ratio is limited to about 2. However, when increasing the speed, improving the performance, reducing the size, and lightening the weight as in recent years, it is necessary for example to form through holes of opening diameters of 20 to 60 μm through thicknesses of 300 μm, so the aspect ratio of the through holes reaches as high as 5 to 15. For through holes of such small diameters and large aspect ratios, use of electroconductive paste containing electroconductive particles of sizes on the order of several μm is impossible in practice in view of the insufficiently small size of the electroconductive particles with respect to the opening diameter and the insufficient fillable aspect ratio.
As opposed to this, the method of filling a copper (Cu)-based material by electroless plating+electroplating is also being tried out (Kazuo Kondo et al., “Hole Filling Copper Plating for High Aspect Ratio Through Electrodes Used for 3D Mounting”, Journal of the Institute of Electronics, vol. 6, no. 7, November 2003 (537-630), p. 596 to 601). This can also handle through holes with large aspect ratios. However, there are the defects that not only is a long time required for filling the through holes, but also copper is poor in bondability with the aluminum (Al) of the secondary interconnects since it is easily oxidizable.
Further, methods using iridium (In) alone, tin (Sn) alone, and gold (Au)-tin (Sn) solder alloys are also being studied (Tatsuo Suemasu et al., “High Aspect Ratio Through Interconnects Formed in Silicon Substrates”, Fujikura Technical Reports, no. 102, April 2002, pp. 53 to 57). However, these have low melting points of less than 300° C., so there is the defect that an anodic bonding processing raising the temperature to over 380° C. at the least cannot be applied for silicon/silicon bonding and glass/silicon bonding.